1. Field of the Invention
The present invention relates to an image processing device including pixel interpolation, such as a pixel interpolation device, a line interpolation device, an image size conversion device and an image interpolation device.
2. Related Art
FIG. 49 is a diagram showing a structure of a pixel interpolation device described in Japanese Patent Laid Open No. H5-68240. A delay circuit 101 extracts pixel data a, b, c, d, e and f, which forming an area of 3×2 dots shown in FIG. 50 from an input pixel data Pin. In FIG. 50, each open circle “∘” represents the pixel data, and each cross “X” represents an interpolation pixel data. In FIG. 50, the interpolation pixel designated by Po is calculated based on a pixel data a, b, d, d, e and f.
A threshold value calculating circuit 103 calculates an average value of the pixel data a, b, c, d, e and f and outputs the calculated average value as a threshold value data SH. The threshold value data SH is sent to a binarization circuit 104. The binarization circuit 104 compares each value of the pixel data a, b, c, d, e and f with the threshold value data SH, thereby producing binarization pixel data l, m, n, x, y and z. If the pixel data is not less than the threshold value data SH, the binarization circuit 104 outputs “1” as the binarization pixel data. Conversely, if the pixel data is less than the threshold value data SH, the binarization circuit 104 outputs “0” as the binarization pixel data. The binarized pixel data l, m, n, x, y and z correspond to the pixel data a, b, c, d, e and f, respectively. The binarized pixel data l, m, n, x, y and z are sent to an interpolation pattern table 105.
The interpolation pattern table 105 outputs an interpolation direction data IS designating one of three interpolation directions, a vertical interpolation, a right slant interpolation and a left slant interpolation. FIG. 51 is a schematic diagram showing the interpolation directions corresponding to the binarized pixel data l, m, n, x, y and z. In FIG. 51, each open circle “∘” represents the binarized pixel data “1”, and each solid circle “●” represents the binarized pixel data “0”, and the interpolation directions are indicated by a vertical line “|” designating vertical interpolation, a slash “/” designating left slant interpolation and back slash “\” designating right slant interpolation. For example, if the binarized pixel data x, y and z are “0”, “0” and “0” (pattern u0), and l, m and n are “1”, “1” and “0” (pattern d6), the interpolation direction data IS designates the right slant interpolation “\”.
As shown in FIG. 49, the interpolation direction data IS is sent to a selector 107. The selector 107 selects two pixel data PU and PD, which are located in the interpolation direction, from the pixel data a, b, c, d, e and f. The pixel data PU and PD are sent to an adder 108.
The adder 108 adds the pixel data PU and PD, and the sum of the pixel data PU and PD are sent to a divider 109. The divider 109 divides the sum, thereby producing the interpolation pixel data Po.
FIG. 52 is a diagram showing relations between the interpolation directions and the pixel data PU and PD which are used to calculate the interpolation pixel data Po. If the interpolation direction data IS designates the vertical interpolation, the interpolation pixel data Po is calculated by averaging the pixel data b and e. If the interpolation direction data IS designates the right slant interpolation, the interpolation pixel data Po is calculated by averaging the pixel data d and c. If the interpolation direction data IS designates the left slant interpolation, the interpolation pixel data Po is calculated by averaging the pixel data a and f.
The pixel interpolation device described above has only three interpolation directions. Consequently, a loss of high frequency components occurs in the pixel interpolation process.